I2C-bus controlled PAL/NTSC TV processor

文件：414.94 Kbytes 頁數(shù)：48 Pages

PHI

PHI

I2C-bus controlled PAL/NTSC TV processor

恩XP

I2C-bus controlled PAL/NTSC TV processor

文件：414.94 Kbytes 頁數(shù)：48 Pages

PHI

PHI

I2C-bus controlled PAL/NTSC TV processor

GENERAL DESCRIPTION\nThe TDA8366 is an I2C-bus controlled PAL/NTSC TV processor. The circuit has been designed for use with the baseband chrominance delay line TDA4665 and for DC-coupled vertical and East-West (EW) output stages. The device can process both CVBS and Y/C input signals and has a linea ? Multistandard vision IF circuit (positive and negative modulation)\n? Video identification circuit in the IF circuit which is independent of the synchronization for stable On Screen Display (OSD) under ‘no-signal’ conditions\n? Source selection with 2 Colour Video Blanking Synchronization (CVBS) i;

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