TDA4VE...ALZQ1中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

1 Features

Processor cores:

? Two C7x floating point, vector DSP, up to 1.0 GHz,

160 GFLOPS, 512 GOPS

? Deep-learning matrix multiply accelerator (MMA),

up to 8 TOPS (8b) at 1.0 GHz

? Vision Processing Accelerators (VPAC) with Image

Signal Processor (ISP) and multiple vision assist

accelerators

? Depth and Motion Processing Accelerators

(DMPAC)

? Dual 64-bit Arm? Cortex?-A72 microprocessor

subsystem at up to 2 GHz

– 1MB shared L2 cache per dual-core Cortex?-

A72 cluster

– 32KB L1 DCache and 48KB L1 ICache per

Cortex?-A72 core

? Up to Six Arm? Cortex?-R5F MCUs at up to 1.0

GHz

– 16K I-Cache, 16K D-Cache, 64K L2 TCM

– Two Arm? Cortex?-R5F MCUs in isolated MCU

subsystem

– Four (TDA4VE) or Two (TDA4AL/TDA4VL)

Arm? Cortex?-R5F MCUs in general compute

partition

? GPU IMG BXS-64-4, 256kB Cache, up to 800

MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and

TDA4VL)

? Custom-designed interconnect fabric supporting

near max processing entitlement

Memory subsystem:

? Up to 4MB of on-chip L3 RAM with ECC and

coherency

– ECC error protection

– Shared coherent cache

– Supports internal DMA engine

? Up to Two External Memory Interface (EMIF)

modules with ECC

– Supports LPDDR4 memory types

– Supports speeds up to 4266 MT/s

– Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-

bit data bus with inline ECC up to 17 GB/s per

EMIF

? General-Purpose Memory Controller (GPMC)

? One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB

on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

? Functional Safety-Compliant targeted (on select

part numbers)

? Developed for functional safety applications

? Documentation available to aid ISO 26262

functional safety system design up to ASIL-D/SIL-3

targeted

? Systematic capability up to ASIL-D/SIL-3 targeted

? Hardware integrity up to ASIL-D/SIL-3 targeted for

MCU Domain

? Hardware integrity up to ASIL-B/SIL-2 targeted for

Main Domain

? Hardware integrity up to ASIL-D/SIL-3 targeted

for Extended MCU (EMCU) portion of the Main

Domain

? Safety-related certification

– ISO 26262 planned

Device security (on select part numbers):

? Secure boot with secure runtime support

? Customer programmable root key, up to RSA-4K

or ECC-512

? Embedded hardware security module

? Crypto hardware accelerators – PKA with ECC,

AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

? One PCI-Express? (PCIe) Gen3 controllers

– Up to four lanes per controller

– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3

(8.0GT/s) operation with auto-negotiation

? One USB 3.0 dual-role device (DRD) subsystem

– Enhanced SuperSpeed Gen1 Port

– Supports Type-C switching

– Independently configurable as USB host, USB

peripheral, or USB DRD

? Two CSI2.0 4L RX plus Two CSI2.04L TX

Automotive interfaces:

? Twenty Modular Controller Area Network (MCAN)

modules with full CAN-FD support

Display subsystem:

? One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L

TX (up to 2.5K)

? One eDP 4L (TDA4VE/TDA4VL)

? One DPI

Audio interfaces:

? Five Multichannel Audio Serial Port (MCASP)

modules

Video acceleration:

? TDA4VE: H.264/H.265 Encode/Decode (up to 480

MP/s)

? TDA4AL: H.264/H.265 Encode only (up to 480

MP/s)

? TDA4VL: H.264/H.265 Encode/Decode (up to 240

MP/s)

Ethernet:

? Two RMII/RGMII interfaces

Flash memory interfaces:

? Embedded MultiMediaCard Interface ( eMMC?

5.1)

? One Secure Digital? 3.0/Secure Digital Input

Output 3.0 interfaces (SD3.0/SDIO3.0)

? Two simultaneous flash interfaces configured as

– One OSPI or HyperBus? or QSPI, and

– One QSPI

System-on-Chip (SoC) architecture:

? 16-nm FinFET technology

? 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA

(ALZ)

Companion Power Management ICs (PMIC):

? Functional Safety-Compliant support up to ASILD

/ SIL-3 targeted

? Flexible mapping to support different use cases

2 Applications

? Advanced Driver Assistance System (ADAS)

? Machine vision

? Industrial transport

? Retail automation

? Surveillance

3 Description

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto? 7 architecture, targeted

at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade

of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both

traditional and deep learning algorithms at industry leading power/performance ratios with a high level of

system integration to enable scalability and lower costs for advanced vision camera applications. Key cores

include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm

accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging

subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security

hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and

EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling

backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning

accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating

at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators

provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm?

Cortex?-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm?

Cortex?-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm? Cortex?-A72

core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes

flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics

applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the

integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To

further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need

for an external system microcontroller.