QorIQ T1024 Reference Design Board

文件：549.92 Kbytes 頁(yè)數(shù)：49 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

Communications Processors

文件：142.85 Kbytes 頁(yè)數(shù)：3 Pages

恩XP

QorIQ T-Series

The 恩XP QorIQ? dual-core T1024 and single-core T1014 communications processors combine 64-bit cores, built on Power Architecture? technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications and industrial

Teledyne e2v

QorIQ T1024 Reference Design Board

文件：549.92 Kbytes 頁(yè)數(shù)：49 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

QorIQ T1024 Reference Design Board

文件：549.92 Kbytes 頁(yè)數(shù)：49 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

QorIQ T1024 Reference Design Board

文件：549.92 Kbytes 頁(yè)數(shù)：49 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

QorIQ, 2xCPU 64-Bit Pwr Arch, 1.0GHz, DDR3L/4, PCIe, 1/10GbE, HW Accel, SEC, 0 to 105C, 23x23 pkg

The QorIQ? dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture? technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications Core Complex? Single and dual e5500 cores, built on Power Architecture technology\n? Up to 1.4 GHz with 64-bit ISA support\n? Three levels of instructions: user, supervisor, hypervisor\n? Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture\n? 256 KB backside L2 cach;

恩XP

QorIQ, 2xCPU 64-Bit Pwr Arch, 1.0GHz, DDR3L/4, PCIe, 1/10GbE, HW Accel,SEC,0 to 105C,DeepSleep,23x23

The QorIQ? dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture? technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications Core Complex? Single and dual e5500 cores, built on Power Architecture technology\n? Up to 1.4 GHz with 64-bit ISA support\n? Three levels of instructions: user, supervisor, hypervisor\n? Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture\n? 256 KB backside L2 cach;

恩XP