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          首頁 >SY100E151>規(guī)格書列表

          型號(hào)下載 訂購功能描述制造商 上傳企業(yè)LOGO

          SY100E151

          6-BIT D REGISTER

          文件:63.16 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151

          Flip Flops, Registers Products

          The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems.The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. ·1100MHz toggle frequency\n·Extended 100E VEE?range of -4.2V to -5.46V\n·Differential outputs\n·Asynchronous Master Reset\n·Dual clocks\n·Fully compatible with industry standard 10KH, 100K ECL levels\n·Internal 75KΩ input pulldown resistors\n·Fully compatible with Motorola MC10E/100E151\n·Available ;

          Microchip

          微芯科技

          SY100E151JC

          6-BIT D REGISTER

          DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

          文件:66.31 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JCTR

          6-BIT D REGISTER

          DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

          文件:66.31 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JI

          6-BIT D REGISTER

          DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

          文件:66.31 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JITR

          6-BIT D REGISTER

          DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

          文件:66.31 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JC

          6-BIT D REGISTER

          文件:63.16 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JC

          6-BIT D REGISTER

          文件:64.129 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JCTR

          6-BIT D REGISTER

          文件:63.16 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          SY100E151JCTR

          6-BIT D REGISTER

          文件:64.129 Kbytes 頁數(shù):4 Pages

          MICREL

          麥瑞半導(dǎo)體

          技術(shù)參數(shù)

          • Description:

            4x4

          • Supply Voltage:

            5

          • Max Data (Gbps):

            3.2

          • Icc (mA):

            200

          • Max Within Device Skew (ps):

            30

          • OE:

            False

          • RPE:

            False

          • FSI:

            False

          • Input Mux:

            True

          • Input EQ:

            False

          • Output Type:

            LVDS

          • Output Voltage:

            2.5V

          供應(yīng)商型號(hào)品牌批號(hào)封裝庫存備注價(jià)格
          SYN
          24+/25+
          37
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          24+
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          25+
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          就找我吧!--邀您體驗(yàn)愉快問購元件!
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          SYNERGY
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          PLCC28L
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          更多SY100E151供應(yīng)商 更新時(shí)間2026-1-19 18:35:00
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