SN74LS93中文資料4 位二進制計數(shù)器數(shù)據(jù)手冊TI規(guī)格書

描述 Description

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93. All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications. To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QA output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the QD output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.

特性 Features

? '90A, 'LS90 . . . Decade Counters
? '92A, 'LS92 . . . Divide By-Twelve Counters
? '93A, 'LS93 . . . 4-Bit Binary Counters
TYPES TYPICAL POWER DISSIPATION '90A 145 mW '92A, '93A 130 mW 'LS90, 'LS92, 'LS93 45 mW

簡介

SN74LS93屬于集成電路（IC）的計數(shù)器除法器。由TI制造生產(chǎn)的SN74LS93計數(shù)器，除法器計數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進行計數(shù)，然后使用多個并行輸出重新發(fā)送累加的計數(shù)，和/或生成單個輸出信號轉(zhuǎn)換，從而對應(yīng)用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進行響應(yīng)。除了簡單的事件計數(shù)，它們還可用于各種頻率合成應(yīng)用。