DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

文件：73.83 Kbytes 頁數(shù)：3 Pages

MOTOROLA

摩托羅拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

文件：73.83 Kbytes 頁數(shù)：3 Pages

MOTOROLA

摩托羅拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

文件：73.83 Kbytes 頁數(shù)：3 Pages

MOTOROLA

摩托羅拉

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：53.28 Kbytes 頁數(shù)：5 Pages

FAIRCHILD

仙童半導(dǎo)體