SN74F161A集成電路（IC）的計數(shù)器除法器規(guī)格書PDF中文資料

SN74F161A屬于集成電路（IC）的計數(shù)器除法器。由德州儀器制造生產(chǎn)的SN74F161A計數(shù)器，除法器計數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進行計數(shù)，然后使用多個并行輸出重新發(fā)送累加的計數(shù)，和/或生成單個輸出信號轉(zhuǎn)換，從而對應用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進行響應。除了簡單的事件計數(shù)，它們還可用于各種頻率合成應用。

Internal Look-Ahead Circuitry for Fast

Counting

Carry Output for N-Bit Cascading

Fully Synchronous Operation for Counting

description

This synchronous, presettable, 4-bit binary

counter has internal carry look-ahead circuitry

for use in high-speed counting designs.

Synchronous operation is provided by having all

flip-flops clocked simultaneously so that the

outputs change coincident with each other when

so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the

output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However,

counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four

flip-flops on the rising (positive-going) edge of CLK.

This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because

presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs

to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.

The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop

outputs to low, regardless of the levels of CLK, LOAD, ENP, and ENT.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without

additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and

ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a

high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used

to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the

operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter

(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold

times.