SN74CBT3384CDGVR集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

SN74CBT3384CDGVR屬于集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器。由德州儀器制造生產(chǎn)的SN74CBT3384CDGVR信號(hào)開關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無(wú)窮變化量。

Undershoot Protection for Off-Isolation on

A and B Ports Up To ?2 V

Bidirectional Data Flow, With Near-Zero

Propagation Delay

Low ON-State Resistance (ron)

Characteristics (ron = 3 Ω Typical)

Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

(Cio(OFF) = 5 pF Typical)

Data and Control Inputs Provide

Undershoot Clamp Diodes

Low Power Consumption

(ICC = 3 μA Max)

VCC Operating Range From 4 V to 5.5 V

Data I/Os Support 0 to 5-V Signaling Levels

(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)

Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

Ioff Supports Partial-Power-Down Mode

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Performance Tested Per JESD 22

? 2000-V Human-Body Model

(A114-B, Class II)

? 1000-V Charged-Device Model (C101)

Supports Both Digital and Analog

Applications: PCI Interface, Memory

Interleaving, Bus Isolation, Low-Distortion

Signal Gating

description/ordering information

The SN74CBT3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),

allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the

SN74CBT3384C provides protection for undershoot up to ?2 V by sensing an undershoot event and ensuring

that the switch remains in the proper OFF state.

The SN74CBT3384C is organized as two 5-bit bus switches with separate output-enable (1OE, 2OE) inputs.

It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus

switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When

OE is high, the associated 5-bit bus switch is OFF, and the high-impedance state exists between the A and B

ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.