DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Controlled Baseline ? One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of ?55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree? 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages

文件：714.6 Kbytes 頁數(shù)：10 Pages

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SN74ACT74-Q1 Automotive Dual D-Type Flip-Flops With Preset and Clear

1 Features ? AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B ? Available in wettable flank QFN package ? Operating voltage range of 4.5V to 5.5V ? TTL-compatible i

文件：1.57567 Mbytes 頁數(shù)：31 Pages

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SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features ? 4.5V to 5.5V VCC operation ? Inputs accept voltages to 5.5V ? Max tpd of 10.5ns at 5V ? Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

文件：2.89926 Mbytes 頁數(shù)：41 Pages

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes 頁數(shù)：6 Pages

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：528.92 Kbytes 頁數(shù)：16 Pages

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.15348 Mbytes 頁數(shù)：21 Pages

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具有清零和預(yù)置端的雙路正邊沿觸發(fā)式 D 型觸發(fā)器

The ?ACT74 dual positive-edge-triggered devices are D-type flip-flops.\n\n A low level at the preset (PRE)\\ or clear (CLR)\\ input sets or resets the outputs, regardless of the levels of the otherinputs. When PRE\\ and CLR\\ are inactive (high), data at the data (D) input meeting the setup-time req ? 4.5-V to 5.5-V VCC Operation\n? Inputs Accept Voltages to 5.5 V\n? Max tpd of 10.5 ns at 5 V\n? Inputs Are TTL-Voltage Compatible;

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絲印：AD74；Package：WQFN(BQA)；SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features ? 4.5V to 5.5V VCC operation ? Inputs accept voltages to 5.5V ? Max tpd of 10.5ns at 5V ? Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

文件：2.89926 Mbytes 頁數(shù)：41 Pages

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絲?。?a target="_blank" title="Marking" href="/act74/marking.html">ACT74；Package：SOIC(D)；SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features ? 4.5V to 5.5V VCC operation ? Inputs accept voltages to 5.5V ? Max tpd of 10.5ns at 5V ? Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

文件：2.89926 Mbytes 頁數(shù)：41 Pages

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絲?。?a target="_blank" title="Marking" href="/ad74/marking.html">AD74；Package：SSOP(DB)；SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features ? 4.5V to 5.5V VCC operation ? Inputs accept voltages to 5.5V ? Max tpd of 10.5ns at 5V ? Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

文件：2.89926 Mbytes 頁數(shù)：41 Pages

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德州儀器