DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages Dependable Texas Instruments Quality and Reliability description The ‘76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The ‘76 is a positive-edge-triggered flip- flo

文件：420.54 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

DUAL JK FLIP-FLOP WITH SET AND CLEAR

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long a

文件：63.62 Kbytes 頁數(shù)：2 Pages

MOTOROLA

摩托羅拉

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

文件：531.82 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54ls76aj/marking.html">SN54LS76AJ；Package：CDIP；DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages Dependable Texas Instruments Quality and Reliability description The ‘76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The ‘76 is a positive-edge-triggered flip- flo

文件：420.54 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

絲印：SN54LS76AJ；Package：CDIP；DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages Dependable Texas Instruments Quality and Reliability description The ‘76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The ‘76 is a positive-edge-triggered flip- flo

文件：420.54 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

文件：477.1 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

文件：531.82 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

具有預(yù)置和清零端的雙路 J-K 觸發(fā)器

The '76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The '76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K ? Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages \n? Dependable Texas Instruments Quality and Reliability;

TI

德州儀器

DUAL JK FLIP-FLOP WITH SET AND CLEAR

恩XP