OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 頁數(shù)：32 Pages

TI

德州儀器

絲印：SN54LS374J；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 頁數(shù)：32 Pages

TI

德州儀器

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE)

文件：250.48 Kbytes 頁數(shù)：7 Pages

MOTOROLA

摩托羅拉

4-BIT D LATCH

The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo

文件：163.97 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

文件：395.7 Kbytes 頁數(shù)：9 Pages

TI

德州儀器

絲印：SN54LS375J；Package：CDIP；4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

文件：395.7 Kbytes 頁數(shù)：9 Pages

TI

德州儀器

4-BIT D LATCH

The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo

文件：163.97 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

絲?。?a target="_blank" title="Marking" href="/sn54ls375j/marking.html">SN54LS375J；Package：CDIP；4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

文件：395.7 Kbytes 頁數(shù)：9 Pages

TI

德州儀器

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar

文件：250.77 Kbytes 頁數(shù)：7 Pages

MOTOROLA

摩托羅拉

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar

文件：250.77 Kbytes 頁數(shù)：7 Pages

MOTOROLA

摩托羅拉