絲印：SN5；Package：SOT23-6；N-Channel 60-V (D-S) MOSFET Low RDS(on) trench technology.

文件：590.35 Kbytes 頁(yè)數(shù)：5 Pages

LRC

樂(lè)山無(wú)線電

絲?。?a target="_blank" title="Marking" href="/sn5400j/marking.html">SN5400J；Package：CDIP；SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates

1 Features 1? Package Options Include: – Plastic Small-Outline (D, NS, PS) – Shrink Small-Outline (DB) – Ceramic Flat (W) – Ceramic Chip Carriers (FK) – Standard Plastic (N) – Ceramic (J) ? Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package ? Inputs Are TTL C

文件：1.69212 Mbytes 頁(yè)數(shù)：38 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn5401j/marking.html">SN5401J；Package：CDIP；QUADRUPLE 2INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS

Package Options include Plastic “Small Qutline’* Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain four independent 2-input NAND gates. The open-collector outputs requ

文件：468.63 Kbytes 頁(yè)數(shù)：12 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn5401j/marking.html">SN5401J；Package：CDIP；QUADRUPLE 2INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS

Package Options include Plastic “Small Qutline’* Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain four independent 2-input NAND gates. The open-collector outputs requ

文件：468.63 Kbytes 頁(yè)數(shù)：12 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54107j/marking.html">SN54107J；Package：CDIP；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

文件：827.19 Kbytes 頁(yè)數(shù)：19 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54107j/marking.html">SN54107J；Package：CDIP；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

文件：827.19 Kbytes 頁(yè)數(shù)：19 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54128j/marking.html">SN54128J；Package：CDIP；LINE DRIVERS

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages Dependable Texas Instruments Quality and Reliability description These devices contain four independent 2-nput-NOR line drivers. Thay perform the Boolean function Y =A T Bory = AB The SN54128 is designed 10 drive

文件：752.38 Kbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54128j/marking.html">SN54128J；Package：CDIP；LINE DRIVERS

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages Dependable Texas Instruments Quality and Reliability description These devices contain four independent 2-nput-NOR line drivers. Thay perform the Boolean function Y =A T Bory = AB The SN54128 is designed 10 drive

文件：752.38 Kbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54173j/marking.html">SN54173J；Package：CDIP；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

文件：966.44 Kbytes 頁(yè)數(shù)：19 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sn54173j/marking.html">SN54173J；Package：CDIP；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

文件：966.44 Kbytes 頁(yè)數(shù)：19 Pages

TI

德州儀器