絲?。?strong>SIO；Package：UQFN(RUT)；LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Application

1 Features ? Provides bidirectional voltage translation with no direction terminal ? Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/ down translation at 50-pF capacitor load ? Supports Ioff, partial power-down mo

文件：2.48097 Mbytes 頁數(shù)：39 Pages

TI

德州儀器

絲?。?strong>SIO；Package：UQFN(RUT)；LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Application

1 Features ? Provides bidirectional voltage translation with no direction terminal ? Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/ down translation at 50-pF capacitor load ? Supports Ioff, partial power-down mo

文件：2.48097 Mbytes 頁數(shù)：39 Pages

TI

德州儀器

絲?。?strong>SIO；Package：UQFN(RUT)；LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Application

1 Features ? Provides bidirectional voltage translation with no direction terminal ? Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/ down translation at 50-pF capacitor load ? Supports Ioff, partial power-down mo

文件：2.48097 Mbytes 頁數(shù)：39 Pages

TI

德州儀器

絲?。?strong>SIO；Package：UQFN(RUT)；LSF0204x 4-Bits Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Application

1 Features ? Provides bidirectional voltage translation with no direction terminal ? Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/ down translation at 50-pF capacitor load ? Supports Ioff, partial power-down mo

文件：2.48097 Mbytes 頁數(shù)：39 Pages

TI

德州儀器

絲印：SIOI；Package：VSSOP；5-V ECL Differential Receiver

1FEATURES · Differential PECL/NECL Receiver · Operating Range – PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V – NECL: VCC = 0 V With VEE = –4.2 V to –5.7 V · 250-ps Propagation Delay · Support for Clock Frequencies >2 GHz · Deterministic Output Value for Open Input Conditions · Built-In Tempe

文件：558.07 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

絲印：SIOI；Package：VSSOP；5-V ECL Differential Receiver

1FEATURES · Differential PECL/NECL Receiver · Operating Range – PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V – NECL: VCC = 0 V With VEE = –4.2 V to –5.7 V · 250-ps Propagation Delay · Support for Clock Frequencies >2 GHz · Deterministic Output Value for Open Input Conditions · Built-In Tempe

文件：558.07 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/sioi/marking.html">SIOI；Package：VSSOP；5-V ECL Differential Receiver

1FEATURES · Differential PECL/NECL Receiver · Operating Range – PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V – NECL: VCC = 0 V With VEE = –4.2 V to –5.7 V · 250-ps Propagation Delay · Support for Clock Frequencies >2 GHz · Deterministic Output Value for Open Input Conditions · Built-In Tempe

文件：558.07 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

KEY FEATURES ? Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/ IEEE 1588 and SETS architectures ? Ultra-low jitter of 95 fs ? Enhanced hitless switching minimizes output phase transients ? Input frequency range: ? External crystal: 48 to 54 MHz ? REF clock: 5

文件：1.71772 Mbytes 頁數(shù)：52 Pages

SKYWORKS

思佳訊

Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-TSC) Clocks

KEY FEATURES ? Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/ IEEE 1588 and SETS architectures ? Ultra-low jitter of 100 fs ? Input frequency range: ? External crystal: 48 to 54 MHz ? REF clock: 5 to 250 MHz ? Diff clock: 8 kHz to 750 MHz ? LVCMOS clock: 8 k

文件：1.63984 Mbytes 頁數(shù)：57 Pages

SKYWORKS

思佳訊

Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs

KEY FEATURES ? One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures ? Input frequency range: ? External crystal: 25-54 MHz ? REF clock: 5-250 MHz ? Diff clock: 8 kHz - 750 MHz ? LVCMOS clock: 1 PPS, 8 kHz - 250 MHz ? Output

文件：1.45121 Mbytes 頁數(shù)：57 Pages

SKYWORKS

思佳訊