PIN-CONTROLLED 1–711 MHZ JITTER CLEANING CLOCK

Features ? Provides jitter attenuation for any clock frequency ? One clock input / two clock outputs ? Input/output frequency range: 1–711 MHz ? Ultra low jitter: 300 fs (12 kHz–20 MHz) typical ? Simple pin control interface ? Selectable loop bandwidth for jitter attenuation: 60 Hz–8.4 k

文件：1.55391 Mbytes 頁數(shù)：46 Pages

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思佳訊

Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 710 MHz and generates two low jitter clock outputs at the same frequency. The cl

文件：341.39 Kbytes 頁數(shù)：50 Pages

SILABS

芯科科技

Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 710 MHz and generates two low jitter clock outputs at the same frequency. The cl

文件：341.39 Kbytes 頁數(shù)：50 Pages

SILABS

芯科科技

PIN-CONTROLLED 1–711 MHZ JITTER CLEANING CLOCK

Features ? Provides jitter attenuation for any clock frequency ? One clock input / two clock outputs ? Input/output frequency range: 1–711 MHz ? Ultra low jitter: 300 fs (12 kHz–20 MHz) typical ? Simple pin control interface ? Selectable loop bandwidth for jitter attenuation: 60 Hz–8.4 k

文件：1.55391 Mbytes 頁數(shù)：46 Pages

SKYWORKS

思佳訊

Si5317 EVALUATION BOARD

文件：825.08 Kbytes 頁數(shù)：20 Pages

MURATA

村田

Jitter Attenuator Clock Multiplier

The Si5317B jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 1 input(s), 2 output(s) and has a maximum frequency output of 350 MHz. The Si53

Skyworks

思佳訊

Jitter Attenuator Clock Multiplier

The Si5317C jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 1 input(s), 2 output(s) and has a maximum frequency output of 200 MHz. The Si53

Skyworks

思佳訊

Package：36-VFQFN 裸露焊盤；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC CLK JITTER CLEANR PROG 36QFN

SKYWORKS

思佳訊

Package：36-VFQFN 裸露焊盤；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC CLK JITTER CLEANR PROG 36QFN

SKYWORKS

思佳訊

Package：36-VFQFN 裸露焊盤；包裝：托盤 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC CLK JITTER CLEANR PROG 36QFN

SKYWORKS

思佳訊