Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Features The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set computer) microprocessor that is upward-compatible with the SH-1, SH-2, and SH-2E at the object code level. The SH2A-FPU has an on-chip floating point unit and the SH-2A does not. The use of 16-bit basic instructions enables co

文件：3.71632 Mbytes 頁數(shù)：501 Pages

RENESAS

瑞薩

32-bit RISC CPU IP

? 32-bit internal data bus ? General-purpose register architecture: 16 32-bit general general-purpose registers ? Register bank for fast interrupt response (15 banks) ? RISC type instruction set: Instruction length: 16 bits / 32 bits mixed, 16-bit basic instruction for improving code effici

文件：764.44 Kbytes 頁數(shù)：1 Pages

RENESAS

瑞薩

32-bit RISC CPU IP

? 32-bit internal data bus ? General-purpose register architecture: 16 32-bit general general-purpose registers ? Register bank for fast interrupt response (15 banks) ? RISC type instruction set: Instruction length: 16 bits / 32 bits mixed, 16-bit basic instruction for improving code effici

文件：764.44 Kbytes 頁數(shù)：1 Pages

RENESAS

瑞薩

Renesas 32-Bit RISC Microcomputer SuperH? RISC engine Family

Renesas

瑞薩

線對(duì)板/線對(duì)線連接器

DLL

德利