| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
XpressFlow 2020 Ethernet Routing Switch Chipset General Description The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also prov 文件:614.2 Kbytes 頁(yè)數(shù):34 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK |
技術(shù)參數(shù)
- Input Signal Bandwidth (min)(MHz):
1.2
- Input Signal Bandwidth (max)(MHz):
60
- PA Architecture:
Class AB
- Paths:
2
- Power Consumption(mW):
2 x 950
- VSUPPLY(V):
1.8
- Features:
Integrated Preamp
- Footprint(mm x mm):
11 x 11
- Package/ Pins:
SAWN QFN/80
- RoHS Available:
See Data Sheet
- Oper. Temp.(°C):
-40 to +100
- Budgetary Price (See Notes):
$68.66 @1k
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
NSC |
25+ |
BGA |
3600 |
大量現(xiàn)貨庫(kù)存,提供一站式服務(wù)! |
詢價(jià) | ||
NS |
25+ |
BGA/鋼 |
18000 |
原廠直接發(fā)貨進(jìn)口原裝 |
詢價(jià) | ||
AMD |
25+ |
BGA |
161 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫(kù)存 本公司只做原裝 可 |
詢價(jià) | ||
MAXIM |
17+ |
QFN80 |
6200 |
100%原裝正品現(xiàn)貨 |
詢價(jià) | ||
NS |
BGA |
231 |
正品原裝--自家現(xiàn)貨-實(shí)單可談 |
詢價(jià) | |||
Maxim |
24+ |
SMD |
17900 |
射頻放大器 |
詢價(jià) | ||
TI |
24+ |
5225 |
詢價(jià) | ||||
NSC |
13+ |
BGA |
1743 |
原裝分銷 |
詢價(jià) | ||
原廠正品 |
23+ |
SMD |
5000 |
原裝正品,假一罰十 |
詢價(jià) | ||
SEMTECH |
1711+ |
SOIC8 |
5800 |
只做原裝進(jìn)口,假一罰十 |
詢價(jià) |
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