Cost-Effective, 2A Sink/Source Bus Termination Regulator

General Description The RT9173C is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

文件：225.03 Kbytes 頁數(shù)：13 Pages

RICHTEK

立锜科技

Package：8-SOIC（0.154"，3.90mm 寬）裸露焊盤；包裝：卷帶（TR） 類別：集成電路（IC） 特殊用途穩(wěn)壓器 描述：IC REG CONV DDR BUS 1OUT 8SOP

Richtek USA Inc.

Cost-Effective, 2A Sink/Source Bus Termination Regulator

General Description The RT9173C is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

文件：225.03 Kbytes 頁數(shù)：13 Pages

RICHTEK

立锜科技

1.5A/3A Bus Termination Regulator

General Description The RT9173/A regulator is designed to convert voltage supplies ranging from 1.6V to 6V into a desired output voltage which adjusted by two external voltage divider resistors. The regulator is capable of sourcing or sinking up to 3A of peak current while regulating an output

文件：198.64 Kbytes 頁數(shù)：10 Pages

RICHTEK

立锜科技

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

General Description The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

文件：223.6 Kbytes 頁數(shù)：13 Pages

RICHTEK

立锜科技