FemtoClock?2 Sub-100fs Universal Frequency Translator

Features ? Jitter below 100fs RMS (10kHz to 20MHz) ? Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC) ? PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Dig

文件：3.21855 Mbytes 頁(yè)數(shù)：100 Pages

RENESAS

瑞薩

FemtoClock?2 Jitter Attenuator or Clock Generator

The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jit ? Jitter below 100fs RMS (10kHz to 20MHz)\n? Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)\n? PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)? ;

Renesas

瑞薩

Package：24-WFQFN 裸露焊盤(pán)；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類(lèi)別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：FEMTOCLOCK 2 SYNTHESIZER \u0026 JITTE

Renesas Electronics America Inc

包裝：散裝 功能：頻率轉(zhuǎn)換器 類(lèi)別：開(kāi)發(fā)板，套件，編程器 評(píng)估和演示板及套件 描述：FEMTOCLOCK 2 EVALUATION KIT

Renesas Electronics America Inc