SINGLE-PHASE SILICON BRIDGE RECTIFIER

文件：40.26 Kbytes 頁數(shù)：1 Pages

CHONGQING

平偉實(shí)業(yè)

VersaClock? 7 可編程抖動(dòng)衰減器系列

RC31xxxA（RC31008A 和 RC31012A）是具有網(wǎng)絡(luò)同步功能的小型抖動(dòng)衰減器，且具有完全集成、低功耗和高性能等特點(diǎn)。該系列支持用于轉(zhuǎn)換器同步的JESD204B/C 以及用于網(wǎng)絡(luò)同步的? 和 SyncE。 RC31xxxA 是一款適合在無線和有線基礎(chǔ)設(shè)施、數(shù)據(jù)中心設(shè)備和儀表裝置應(yīng)用中驅(qū)動(dòng)轉(zhuǎn)換器電路的理想時(shí)鐘晶片選擇。這是一款屬于瑞薩電子的高性能 VersaClock? 7 系列的時(shí)鐘晶片。\n\n多達(dá) 27 種配置可在多種設(shè)計(jì)中重復(fù)使用，可儲存在晶片上一次性可編程 (OTP) 儲存器或外部 I2C EEPROM 中。也可以支持備用輸入時(shí)，鐘在需要時(shí)用作參考時(shí)鐘。 ? 1.8V/2.5V/3.3V 靈活工作電壓\n? 具有集成震蕩晶體 5/8/12 路輸出的選項(xiàng)\n? 1kHz-200MHz LVCMOS 輸出\n? 符合 PCIe Gen5/6 標(biāo)準(zhǔn)\n? JESD204B/C 支持帶 DC 耦合或 AC 耦合的差分或單端輸出\n? 集成震蕩晶體進(jìn)而節(jié)省空間并實(shí)現(xiàn) BOM 優(yōu)化\n? 適合同步的乙太網(wǎng)應(yīng)用符合 ITU-T G.8262 和 G.82621 標(biāo)準(zhǔn)\n;

Renesas

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩

VersaClock 7 Programmable Jitter Attenuator Family

Features ? 169fs RMS typical phase jitter ? PCIe? Gen6 Common Clock (CC) 27fs RMS ? Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ? Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ? 1kHz to 650MHz LVDS/LP-HCSL outputs

文件：1.99475 Mbytes 頁數(shù)：65 Pages

RENESAS

瑞薩