PCIe Gen6 4-Output Clock Buffer

The RC19004 is a 4-output PCIe Gen6 buffer that is backward compatible to earlier PCIe generations. The RC19004 provides ultra-low additive jitter and reduced in-to-out delay performance for better design-margin and incorporates several features for easier and more robust design. ? LP-HCSL outputs eliminate up to 16 terminated resistors\n? PCIe Gen 1–6 compliance\n? Drive both source-terminated and double-terminated loads\n? Selectable output slew rate via pin\n? Support both 85Ω and 100Ω output impedance versions\n? Open-drain LOS (Loss-Of-Signal) indication output\n? Power;

Renesas

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PCIe Gen5/6 Fanout Buffer Family with LOS

Features ? PCIe Gen5 additive phase jitter: 6fs RMS ? PCIe Gen6 additive phase jitter: 4fs RMS ? DB2000Q additive phase jitter: 10fs RMS ? 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz ? Power Down Tolerant (PDT) inputs ? Flexible Startup Sequencing (FSS) ? Automatic Clock Pa

文件：2.80466 Mbytes 頁數(shù)：109 Pages

RENESAS

瑞薩

PCIe Gen5/6 Fanout Buffer Family with LOS

Features ? PCIe Gen5 additive phase jitter: 6fs RMS ? PCIe Gen6 additive phase jitter: 4fs RMS ? DB2000Q additive phase jitter: 10fs RMS ? 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz ? Power Down Tolerant (PDT) inputs ? Flexible Startup Sequencing (FSS) ? Automatic Clock Pa

文件：2.80466 Mbytes 頁數(shù)：109 Pages

RENESAS

瑞薩

PCIe Gen5/6 Fanout Buffer Family with LOS

Features ? PCIe Gen5 additive phase jitter: 6fs RMS ? PCIe Gen6 additive phase jitter: 4fs RMS ? DB2000Q additive phase jitter: 10fs RMS ? 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz ? Power Down Tolerant (PDT) inputs ? Flexible Startup Sequencing (FSS) ? Automatic Clock Pa

文件：2.80466 Mbytes 頁數(shù)：109 Pages

RENESAS

瑞薩

PCIe Gen5/6 Fanout Buffer Family with LOS

Features ? PCIe Gen5 additive phase jitter: 6fs RMS ? PCIe Gen6 additive phase jitter: 4fs RMS ? DB2000Q additive phase jitter: 10fs RMS ? 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz ? Power Down Tolerant (PDT) inputs ? Flexible Startup Sequencing (FSS) ? Automatic Clock Pa

文件：2.80466 Mbytes 頁數(shù)：109 Pages

RENESAS

瑞薩

包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC

Renesas Electronics America Inc

包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC

Renesas Electronics America Inc