絲?。?strong>QL30；Package：SOT-23；TPS3840-Q1 Automotive Nano IQ Voltage Supervisor With MR and Programmable Delay

1 Features 1? Qualified for automotive applications ? AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature – Device HBM ESD classification level 2 – Device CDM ESD classification level C7B ? Wide operating voltage : 1.5 V

文件：1.69458 Mbytes 頁數(shù)：37 Pages

TI

德州儀器

絲?。?strong>QL30；Package：SOT-23；TPS3840-Q1 Automotive Nano IQ Voltage Supervisor With MR and Programmable Delay

文件：1.74305 Mbytes 頁數(shù)：37 Pages

TI

德州儀器

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

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60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

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60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

ETCList of Unclassifed Manufacturers

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60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

ETCList of Unclassifed Manufacturers

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60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

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60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：239.12 Kbytes 頁數(shù)：14 Pages

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25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

[QUICK LOGIC] Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme

文件：528.06 Kbytes 頁數(shù)：17 Pages

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