AAL1 Segmentation And Reassembly Processor

Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II?) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data,

文件：2.30048 Mbytes 頁數(shù)：223 Pages

PMC

AAL1 Segmentation And Reassembly Processor

PMC-Sierra

AAL1 Segmentation And Reassembly Processor

Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II?) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data,

文件：2.30048 Mbytes 頁數(shù)：223 Pages

PMC

AAL1 Segmentation And Reassembly Processor

Description\nThe AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II?) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, an Circuit Interface Features\n? Provides AAL1 segmentation and reassembly of eight 2 Mbit/s data streams or one 45 Mbit/s or less data stream.\n? Supports 256 Virtual Channels (VCs) (32 per line).\n? Supports n × 64 structured data format.\n? Supports arbitrary timeslot-to-VC mappings, including alter;

PMC-Sierra