PL133-67中文資料Buffers數(shù)據(jù)手冊Microchip規(guī)格書

描述 Description

The PL133-67 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-67 accepts a reference clock input from DC to 150MHz and provides 6 outputs of the same frequency.The PL133-67 is offered in a TSSOP-16L package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC.The PL133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.

特性 Features

? 1:6 LVCMOS output fanout buffer for DC to150MHz
? 8mA Output Drive Strength
? Low power consumption for portable applications
? Low input-output delay
? Output-Output skew less than 250ps
? Low Additive Phase Jitter of 60fs RMS
? 2.5V to 3.3V ±10% operation
? Operating temperature range from -40°C to 85°C
? Available in 16-Pin SOP GREEN/RoHS package

簡介

PL133-67屬于集成電路（IC）的時鐘緩沖器驅(qū)動器。由Microchip制造生產(chǎn)的PL133-67時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負(fù)載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。