TrenchMOS transistor Logic level FET

GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP65N06LT is sup

文件：71.46 Kbytes 頁數(shù)：9 Pages

PHI

PHI

isc N-Channel MOSFET Transistor

FEATURES ·Drain Current -ID= 63A@ TC=25℃ ·Drain Source Voltage -VDSS= 55V(Min) ·Static Drain-Source On-Resistance -RDS(on) = 16mΩ(Max)@VGS= 10V DESCRIPTION ·DC-to-DC Converter ·General Industrial Applications ·Power Motor Control

文件：371.72 Kbytes 頁數(shù)：2 Pages

ISC

無錫固電

TrenchMOS? transistor Logic level FET

GENERAL DESCRIPTION\nN-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.\nThe PHP65N06LT is suppl ? ’Trench’ technology\n? Very low on-state resistance\n? Fast switching\n? Stable off-state characteristics\n? High thermal cycling performance\n? Low thermal resistance;

恩XP

isc N-Channel MOSFET Transistor

FEATURES ·Drain Current -ID= 63A@ TC=25℃ ·Drain Source Voltage -VDSS= 55V(Min) ·Static Drain-Source On-Resistance -RDS(on) = 18mΩ(Max)@VGS= 10V DESCRIPTION ·DC-to-DC Converter ·General Industrial Applications ·Power Motor Control

文件：372.2 Kbytes 頁數(shù)：2 Pages

ISC

無錫固電

TrenchMOS transistor Standard level FET

GENERAL DESCRIPTION N-channel enhancement mode standard level field-effect power transistor in a plastic envelope using ’trench’ technology. The device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in DC-DC converters a

文件：64.629 Kbytes 頁數(shù)：8 Pages

PHI

PHI