128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description The μPD45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 2,097,152 ×16 ×4 (word ×bit ×bank). The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the posit

文件：701.15 Kbytes 頁數(shù)：87 Pages

ELPIDA

爾必達

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description\nThe μPD45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 2,097,152 ×16 ×4 (word ×bit ×bank). The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive ?Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge\n?Pulsed interface\n?Possible to assert random column address in every cycle\n?Quad internal banks controlled by BA0(A13) and BA1(A12)\n?Byte control by LDQM and UDQM\n?Programmable Wrap sequence (Sequential / Inter;

Micron

美光

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description The μPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. Features ? Fully Synchronous Dynamic RAM, with all signals referenc

文件：713.62 Kbytes 頁數(shù)：89 Pages

ELPIDA

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128M-bit Synchronous DRAM 4-bank, LVTTL

Description The μPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pi

文件：1.10737 Mbytes 頁數(shù)：92 Pages

NEC

瑞薩

128M-bit Synchronous DRAM 4-bank, LVTTL

文件：932.36 Kbytes 頁數(shù)：86 Pages

ELPIDA

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