18M-BIT DDR II SRAM 4-WORD BURST OPERATION

文件：511.25 Kbytes 頁數(shù)：33 Pages

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18M-BIT DDR II SRAM 4-WORD BURST OPERATION

Renesas

瑞薩

18M-BIT DDR II SRAM 4-WORD BURST OPERATION

文件：511.25 Kbytes 頁數(shù)：33 Pages

RENESAS

瑞薩

18M-BIT DDR II SRAM 4-WORD BURST OPERATION

Features ? 1.8 ± 0.1 V power supply ? 165-pin PLASTIC BGA (13 x 15) ? HSTL interface ? PLL circuitry for wide output data valid window and future frequency scaling ? Pipelined double data rate operation ? Common data input/output bus ? Two-tick burst for low DDR transaction size ? Two inpu

文件：499.47 Kbytes 頁數(shù)：33 Pages

RENESAS

瑞薩

18M-BIT DDR II SRAM 4-WORD BURST OPERATION

Features ? 1.8 ± 0.1 V power supply ? 165-pin PLASTIC BGA (13 x 15) ? HSTL interface ? PLL circuitry for wide output data valid window and future frequency scaling ? Pipelined double data rate operation ? Common data input/output bus ? Two-tick burst for low DDR transaction size ? Two inpu

文件：499.47 Kbytes 頁數(shù)：33 Pages

RENESAS

瑞薩