8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters

General description The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been

文件：337.14 Kbytes 頁數(shù)：71 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

General description The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been

文件：366.01 Kbytes 頁數(shù)：75 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

General description The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been

文件：366.01 Kbytes 頁數(shù)：75 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters

General description The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been

文件：337.14 Kbytes 頁數(shù)：71 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable

文件：650.61 Kbytes 頁數(shù)：94 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable

文件：650.61 Kbytes 頁數(shù)：94 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable Flash with 8-bit ADCs

文件：372.25 Kbytes 頁數(shù)：75 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable Flash with 8-bit ADCs

文件：372.25 Kbytes 頁數(shù)：75 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable Flash with 8-bit ADCs

文件：372.25 Kbytes 頁數(shù)：75 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

Overview The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporat 2.1 Principal features\n4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.\n256-byte RAM data memory. P89LPC9351 and P89LPC9361 also include a 512-byte auxiliary on-chip RAM.\n;

恩XP