8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM

General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorpor

文件：314.62 Kbytes 頁數(shù)：63 Pages

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PHI

8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM

General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorpor

文件：326.7 Kbytes 頁數(shù)：66 Pages

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8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM

General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorpor

文件：326.7 Kbytes 頁數(shù)：66 Pages

恩XP

8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM

General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorpor

文件：314.62 Kbytes 頁數(shù)：63 Pages

PHI

PHI

8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM

OverviewThe P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P \n\nPrincipal features\n\n\n\n?1 kB byte-erasable flash code memory organized into 256 B sectors and 16 B pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.\n\n?128 B RAM data memory.\n\n?Two 16-bit counter/timers. Each timer may be configured to toggle a port out;

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