Passivated Assembled Circuit Elements, 25 A

DESCRIPTION The P100 series of integrated power circuits consists of power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs are greatly simplified giving advantages of cost reduction and reduced size. Applications include power supplie

文件：179.52 Kbytes 頁數(shù)：6 Pages

VISHAYVishay Siliconix

威世威世科技公司

PASSIVATED ASSEMBLED CIRCUIT ELEMENTS

Description The P100 series of Integrated Power Circuits consists of power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs are greatly simpli fied giving advantages of cost reduction and reduced size. Applications include power suppli

文件：82.66 Kbytes 頁數(shù)：7 Pages

IRF

PASSIVATED ASSEMBLED CIRCUIT ELEMENTS

Description The P100 series of Integrated Power Circuits consists of power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs are greatly simpli fied giving advantages of cost reduction and reduced size. Applications include power suppli

文件：82.66 Kbytes 頁數(shù)：7 Pages

IRF

無線壓力傳感器節(jié)點P102

一種新型的數(shù)據(jù)采集系統(tǒng)，該系統(tǒng)基于BeeLPW協(xié)議，可以自組織形成星型網(wǎng)絡(luò)拓撲結(jié)構(gòu)。使用簡單方便，無線數(shù)字信號傳輸方式消除了長電纜傳輸帶來的噪聲干擾，整個測量系統(tǒng)具有極高的測量精度和抗干擾能力。無線傳感器節(jié)點可以組成龐大的無線傳感器網(wǎng)絡(luò)，支持上百個測點同時進行測試。 節(jié)點結(jié)構(gòu)緊湊，體積小巧，便于安裝；? 測壓范圍0~25MPa；? 采集的數(shù)據(jù)既可以實時無線傳輸至計算機；? 節(jié)點的空中傳輸速率最大可以達到200K bps，有效室外通訊距離可達200m;

Beetech

必創(chuàng)

single- and dual-core communications processors

Overview The QorIQ mid-performance tier, which includes the P2020 (dual-core processor) and P2010 (single-core processor) communications processors, delivers high single-threaded performance per watt for a wide variety of applications in the networking, telecom, military and industrial markets.

文件：227.66 Kbytes 頁數(shù)：2 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

Low Skew Output Buffer

DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu

文件：206.13 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu

文件：206.13 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：236.44 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：236.44 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：222.99 Kbytes 頁數(shù)：6 Pages

PLL