single- and dual-core communications processors

Overview The QorIQ mid-performance tier, which includes the P2020 (dual-core processor) and P2010 (single-core processor) communications processors, delivers high single-threaded performance per watt for a wide variety of applications in the networking, telecom, military and industrial markets.

文件：227.66 Kbytes 頁數(shù)：2 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

Low Skew Output Buffer

DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu

文件：206.13 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu

文件：206.13 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：236.44 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：236.44 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：222.99 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o

文件：222.99 Kbytes 頁數(shù)：6 Pages

PLL

single- and dual-core communications processors

Freescale QorIQ communications platforms are the next-generation evolution of our leading PowerQUICC communications processors. Built using high-performance Power Architecture? cores, QorIQ platforms enable a new era of networking innovation where the reliability, security and quality of service f

文件：291.73 Kbytes 頁數(shù)：2 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

文件：180.37 Kbytes 頁數(shù)：6 Pages

PLL

Voltage Monitoring Relays

Description The HLVA6I23 is a single-phase undervoltage monitor designed to protect sensitive equipment from brownout or undervoltage conditions. Time delays are included to prevent nuisance tripping and short cycling. The 30A, 1hp rated, SPDT relay contacts allow direct control of motors, so

文件：456.27 Kbytes 頁數(shù)：2 Pages

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