P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：78.68 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

P-Channel Logic Level Enhancement Mode Field Effect Transistor

ONSEMI

安森美半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/.39k/marking.html">.39K；Package：SOT-23；P-Channel Mosfet

Application Load/Power Switching Interfacing Switching Logic Level Shift

文件：1.54866 Mbytes 頁數(shù)：4 Pages

TECHPUBLIC

臺(tái)舟電子

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：78.68 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

P-Channel Logic Level Enhancement Mode Field Effect Transistor

文件：456.46 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

P-Channel 20-V (D-S) MOSFET

文件：1.035609 Mbytes 頁數(shù)：9 Pages

VBSEMI

微碧半導(dǎo)體

P 溝道邏輯電平增強(qiáng)型場(chǎng)效應(yīng)晶體管，-20V，-1A，0.41Ω

這些P溝道邏輯電平增強(qiáng)模式功率場(chǎng)效應(yīng)晶體管采用飛兆專有的高密度DMOS技術(shù)生產(chǎn)。 這種密度非常高的工藝是專為最大限度地降低通態(tài)電阻而定制的。 這些器件特別適合筆記本電腦電源管理、便攜電子產(chǎn)品及其他電池供電電路等低電壓應(yīng)用，此類應(yīng)用需要在很小尺寸的表面貼裝封裝中實(shí)現(xiàn)快速高端開關(guān)和低線內(nèi)功率損耗。 ?-1 A, -20 V, RDS(ON) = 0.41Ω @ VGS= -2.7 V, RDS(ON) = 0.3 Ω @ VGS = -4.5 V.\n?柵極驅(qū)動(dòng)電平要求極低，從而可在3V電路中直接運(yùn)行。 VGS(th) < 1.0V。\n?專有封裝設(shè)計(jì)使用銅引線框架，可提供出色的熱和電氣能力。\n?高密度單元設(shè)計(jì)，可實(shí)現(xiàn)極低的RDS(ON)。\n?出色的導(dǎo)通阻抗和最大的DC電流能力。\n?緊湊型工業(yè)標(biāo)準(zhǔn)SOT-23表面貼裝封裝。;

ONSEMI

安森美半導(dǎo)體