P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：56.6 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

P-Channel 30-V (D-S) MOSFET

文件：967.26 Kbytes 頁數(shù)：8 Pages

VBSEMI

微碧半導(dǎo)體

P 溝道邏輯電平增強型場效應(yīng)晶體管，-30V，-30A，42mΩ

這些P溝道邏輯電平增強模式功率場效應(yīng)晶體管采用飛兆專有的高密度DMOS技術(shù)生產(chǎn)。 這種密度非常高的工藝是專為最大限度地降低導(dǎo)通阻抗而定制的。 這些器件特別適合需要快速開關(guān)、低線路內(nèi)功率損耗以及抗瞬變能力的DC/DC轉(zhuǎn)換器和高效率開關(guān)電路等低電壓應(yīng)用。 -30 A，-30 V。 RDS(ON) = 0.042 Ω @ VGS= -4.5 V，RDS(ON) = 0.025 Ω @ VGS= -10 V。\n 在高溫下額定的臨界DC電氣參數(shù)。\n 耐用的內(nèi)部源極-漏極二極管使得無需使用外部齊納二極管瞬態(tài)抑制器。\n 高密度單元設(shè)計，可實現(xiàn)極低的RDS(ON)。\n 175°C最大結(jié)溫額定值。;

ONSEMI

安森美半導(dǎo)體

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：357.86 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

N-Channel Enhancement Mode Field Effect Transistor

文件：56.17 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：56.6 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體