P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching pe

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FAIRCHILD

仙童半導(dǎo)體

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching p

文件：167.43 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

isc P-Channel MOSFET Transistor

FEATURES ·Drain Current -ID= -24A@ TC=25℃ ·Drain Source Voltage -VDSS= -20V(Min) ·Static Drain-Source On-Resistance -RDS(on) = 50mΩ(Max)@VGS= 10V DESCRIPTION ·Motor drive, DC-DC converter, power switch and solenoid drive.

文件：344.29 Kbytes 頁數(shù)：2 Pages

ISC

無錫固電

P 溝道，邏輯電平增強(qiáng)型場效應(yīng)晶體管，-20V，-24A，50mΩ

這些邏輯電平P溝道增強(qiáng)模式功率場效應(yīng)晶體管采用飛兆專有的高密度DMOS技術(shù)生產(chǎn)。 這種密度非常高的工藝是專為最大限度地降低通態(tài)電阻，提供卓越的開關(guān)性能，以及在雪崩和交換模式下承受高能量脈沖而定制的。 這些器件特別適合需要快速開關(guān)、低線路內(nèi)功率損耗以及抗瞬變能力的汽車、DC/DC轉(zhuǎn)換器、PWM電機(jī)控制和其他電池供電電路等低電壓應(yīng)用。 -24 A, -20 VrDS(ON) = 50 mΩ @ VGS = -4.5 VrDS(ON) = 70 mΩ @ VGS = -2.7 VrDS(ON) = 75 mΩ @ VGS = -2.5 V\nCritical DC Electrical Parameters Specified at Elevated Temperature\nRuggedInternal Source-Drain Diode Can Eliminate The Need For An External Zener Diode Transient Suppressor\n175°C Maximum Juncti;

ONSEMI

安森美半導(dǎo)體