2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ?1/2/4/8, ?2/4/8/16 Clock Divider

文件：94.15 Kbytes 頁數(shù)：12 Pages

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2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider

文件：104.86 Kbytes 頁數(shù)：13 Pages

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2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT

文件：147.42 Kbytes 頁數(shù)：12 Pages

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2.5 V / 3.3 V Any Differential Clock In to Differential LVPECL Out

The NB6L239 is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; divide 1/2/4/8 and divide 2/4/8/16. Both divider circuits drive a pair of LVPECL outputs ? Maximum Clock Input Frequency; ≥ 3GHz\n? Input compatibility with LVDS/LVPECL/CML/HSTL\n? 70 ps Typical Rise/Fall Times\n? 5 ps Typcial Output-to-Output Skew\n? Ex. 622.08MHz Input Generates 38.88MHz to 622.08 MHz Outputs\n? Internal 50 Ω Termination Provided\n? Random Clock Jitter ≤

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2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider

文件：104.86 Kbytes 頁數(shù)：13 Pages

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2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT

文件：147.42 Kbytes 頁數(shù)：12 Pages

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2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ?1/2/4/8, ?2/4/8/16 Clock Divider

文件：94.15 Kbytes 頁數(shù)：12 Pages

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2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider

文件：104.86 Kbytes 頁數(shù)：13 Pages

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NB6L239MNEVB Evaluation Board Users Manual

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2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT

文件：147.42 Kbytes 頁數(shù)：12 Pages

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安森美半導(dǎo)體