2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination

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2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop

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帶差分重置和輸入端接的 2.5 至 5.5 V ECL D 觸發(fā)器

The NB4L52 is a differential Data and Clock D flip?flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferre ? Maximum Input Clock Frequency > 4 GHz Typical\n? 145 ps Typical Rise and Fall Times\n? Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V;

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2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination

文件：135.01 Kbytes 頁數(shù)：8 Pages

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2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop

文件：149.6 Kbytes 頁數(shù)：8 Pages

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2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop

文件：149.6 Kbytes 頁數(shù)：8 Pages

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安森美半導體

2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination

文件：135.01 Kbytes 頁數(shù)：8 Pages

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安森美半導體

2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination

文件：135.01 Kbytes 頁數(shù)：8 Pages

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2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop

文件：149.6 Kbytes 頁數(shù)：8 Pages

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Package：16-VFQFN 裸露焊盤；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：復位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 1BIT 16QFN

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