Quad D-type flip-flop 3-State

DESCRIPTION The 74F173 is a high speed 4–bit parallel load register with clock enable control, 3–state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low–to–high clock (CP) tra

文件：88.51 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Quad D-type flip-flop 3-State

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Quad D-type flip-flop 3-State

DESCRIPTION The 74F173 is a high speed 4–bit parallel load register with clock enable control, 3–state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low–to–high clock (CP) tra

文件：88.51 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Quad D-type flip-flop 3-State

DESCRIPTION The 74F173 is a high speed 4–bit parallel load register with clock enable control, 3–state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low–to–high clock (CP) tra

文件：88.51 Kbytes 頁數(shù)：10 Pages

PHI

PHI