T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

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ZARLINK

Zarlink Semiconductor Inc

T1/E1/OC3 System Synchronizer

Description\nThe MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing\nand synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links.\nThe MT9045 generates ST-BUS clock and framing signals that are phase lo ? Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces\n? Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces\n? Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces\n? Supports ETSI E;

Microchip

微芯科技

Package：48-BSSOP（0.295"，7.50mm 寬）；包裝：卷帶（TR） 功能：數(shù)字鎖相環(huán) 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 48SSOP

MICROCHIP

微芯科技

Package：48-BSSOP（0.295"，7.50mm 寬）；包裝：卷帶（TR） 功能：數(shù)字鎖相環(huán) 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 48SSOP

MICROCHIP

微芯科技