T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

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MITEL

T1/E1 System Synchronizer

Description\nThe MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links.\nThe MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048M ? Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces\n? Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces\n? Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals\n? Provides C1.5, C2, C3, C4, C8 and C16 outpu;

Mitel

Package：28-LCC（J 形引線）；包裝：托盤 功能：數(shù)字鎖相環(huán) 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 28PLCC

MICROCHIP

微芯科技

Package：28-LCC（J 形引線）；包裝：卷帶（TR） 功能：數(shù)字鎖相環(huán) 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 28PLCC

MICROCHIP

微芯科技