4 MEG x 4 EDO DRAM

GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the col

文件：291.14 Kbytes 頁(yè)數(shù)：23 Pages

MICRON

美光

4 MEG x 4 EDO DRAM

GENERAL DESCRIPTION\nThe 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the colum ? Industry-standard x4 pinout, timing, functions and packages\n? State-of-the-art, high-performance, low-power CMOS silicon-gate process\n? Single power supply (+3.3V ±0.3V or +5V ±10%)\n? All inputs, outputs and clocks are TTL-compatible\n? Refresh modes: RAS#-ONLY, HIDDEN and CAS#-BEFORE-RAS# ;

Micron

美光

4 MEG x 4 EDO DRAM

GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the col

文件：291.14 Kbytes 頁(yè)數(shù)：23 Pages

MICRON

美光

4 MEG x 4 EDO DRAM

GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the col

文件：291.14 Kbytes 頁(yè)數(shù)：23 Pages

MICRON

美光

4 MEG x 4 EDO DRAM

GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the col

文件：291.14 Kbytes 頁(yè)數(shù)：23 Pages

MICRON

美光

4 MEG x 4 EDO DRAM

GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the col

文件：291.14 Kbytes 頁(yè)數(shù)：23 Pages

MICRON

美光

DRAM

Micron

美光