首頁(yè) >MT46V128M4>規(guī)格書列表
| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
MT46V128M4 | DOUBLE DATA RATE DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:2.55598 Mbytes 頁(yè)數(shù):68 Pages | MICRON 美光 | MICRON | |
MT46V128M4 | 512Mb: x4, x8, x16 Double Data Rate SDRAM Features Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:1.66163 Mbytes 頁(yè)數(shù):93 Pages | MICRON 美光 | MICRON | |
MT46V128M4 | 512Mb: x4, x8, x16 Double Data Rate (DDR) SDRAM SDRAM Features 文件:1.66163 Mbytes 頁(yè)數(shù):93 Pages | MICRON 美光 | MICRON | |
MT46V128M4 | 512Mb: x4, x8, x16 DDR SDRAM Features 文件:3.76267 Mbytes 頁(yè)數(shù):91 Pages | MICRON 美光 | MICRON | |
MT46V128M4 | DOUBLE DATA RATE DDR SDRAM | Micron 美光 | Micron | |
DOUBLE DATA RATE DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:2.55598 Mbytes 頁(yè)數(shù):68 Pages | MICRON 美光 | MICRON | ||
DOUBLE DATA RATE DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:2.55598 Mbytes 頁(yè)數(shù):68 Pages | MICRON 美光 | MICRON | ||
DOUBLE DATA RATE DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:2.55598 Mbytes 頁(yè)數(shù):68 Pages | MICRON 美光 | MICRON | ||
DOUBLE DATA RATE DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:2.55598 Mbytes 頁(yè)數(shù):68 Pages | MICRON 美光 | MICRON | ||
DOUBLE DATA RATE DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce 文件:2.55598 Mbytes 頁(yè)數(shù):68 Pages | MICRON 美光 | MICRON |
技術(shù)參數(shù)
- Data Rate:
DDR400B
- Density:
512Mb
- FBGA Code:
D9MLZ
- Op. Temp.:
0C to +70C
- Part Status:
Production
- PLP:
No
- PLP Start Date:
N/A
- Width:
x4
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
MT |
24+ |
TSSOP |
305 |
詢價(jià) | |||
Micron |
17+ |
6200 |
詢價(jià) | ||||
MICRON |
23+ |
TSOP-66 |
5000 |
原裝正品,假一罰十 |
詢價(jià) | ||
MICRON |
2016+ |
FBGA60 |
9000 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價(jià) | ||
MICRON |
24+ |
TSOP66 |
5000 |
只做原裝公司現(xiàn)貨 |
詢價(jià) | ||
MICRON |
25+ |
FBGA |
2789 |
原裝優(yōu)勢(shì)!絕對(duì)公司現(xiàn)貨! |
詢價(jià) | ||
MICRON |
新 |
972 |
全新原裝 貨期兩周 |
詢價(jià) | |||
MICRONTECHNO |
23+ |
NA |
13650 |
原裝正品,假一罰百! |
詢價(jià) | ||
MICRON |
25+23+ |
TSSOP |
33776 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
MICRON |
17+ |
FBGA60 |
60000 |
保證進(jìn)口原裝可開17%增值稅發(fā)票 |
詢價(jià) |
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