DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 頁(yè)數(shù)：68 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 頁(yè)數(shù)：68 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 頁(yè)數(shù)：68 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 頁(yè)數(shù)：68 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 頁(yè)數(shù)：68 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write acce

文件：2.55598 Mbytes 頁(yè)數(shù)：68 Pages

MICRON

美光

DOUBLE DATA RATE (DDR) SDRAM

General Description The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad bank DRAM. Features ?VDD= +2.5V ±0.2V, VDDQ = +2.5V ±0.2V ? Bidirectional data strobe (DQS) transmitted/received with data, i.

文件：2.35495 Mbytes 頁(yè)數(shù)：74 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

GENERAL DESCRIPTION The DDR333 SDRAM is a high-speed CMOS, dy namic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture. FEATURES

文件：152.46 Kbytes 頁(yè)數(shù)：8 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

GENERAL DESCRIPTION The DDR333 SDRAM is a high-speed CMOS, dy namic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture. FEATURES

文件：152.46 Kbytes 頁(yè)數(shù)：8 Pages

MICRON

美光

DOUBLE DATA RATE DDR SDRAM

GENERAL DESCRIPTION The DDR333 SDRAM is a high-speed CMOS, dy namic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture. FEATURES

文件：152.46 Kbytes 頁(yè)數(shù)：8 Pages

MICRON

美光