MPC860DEVR50D4中文資料PowerQUICC, 32 Bit Power Architecture SoC, 50MHz, CPM, ENET, HDLC, PCMCIA, 0 to 95C數(shù)據(jù)手冊(cè)恩XP規(guī)格書(shū)

描述 Description

The MPC860 PowerQUICC? offers an integrated processor and peripheral solution that can be used in a variety of communications and networking controller applications.
Delivers higher performance in all areas of device operation including flexibility, extensions in capability, and integration
Provides lower power consumption than traditional architectures
Backed by strong third-party tool support through Our Design Alliance Program

特性 Features

Embedded MPC8xx Core with 88 MIPS at 66 MHz (using Dhrystone 2.1); MPC860P - 106 MIPS at 80 MHz for the MPC860P
? 4Kb Instruction Cache; MPC860P - 16Kb Instruction Cache
? 4Kb Data Cache; MPC860P - 8Kb Data Cache
? 8Kb Dual Port RAM
? Instruction and Data MMUs
? Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
? 32 Address Lines
? Complete Static Design (040 MHz Operation)
? Memory Controller (Eight Banks)
? General-Purpose Timers
? System Integration Unit (SIU)
? Interrupts
? Communications Processor Module (CPM)
? Four Baud Rate Generators
? Four SCCs (Serial Communication Controllers)
? Two SMCs (Serial Management Channels)
? One SPI (Serial Peripheral Interface)
? One I2C (Inter-Integrated Circuit) Port
? Time-Slot Assigner
? Parallel Interface Port
? PCMCIA Interface
? Low Power Support
? Debug Interface
? 3.3 V Operation with 5V TTL Compatibility

應(yīng)用 Application

Secure Transaction and Retail Payments
?POS Printer