PowerQUICC??Family Hardware Specifications

文件：1.02468 Mbytes 頁數(shù)：80 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

PowerQUICC??Family Hardware Specifications

文件：1.02468 Mbytes 頁數(shù)：80 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

Hardware Specifications

文件：1.97917 Mbytes 頁數(shù)：80 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

PowerQUICC, 32 Bit Power Architecture SoC, 66MHz, CPM, ENET, ATM, HDLC, PCMCIA, -40 to 95C

The MPC855T is a versatile one-chip integrated microprocessor and peripheral combination designed for lower cost access equipment that requires fast ethernet support capable of 100 Mbps. This member of the MPC860 PowerQUICC? family combines an MPC8xx core processor along with 恩XP? Semiconductors's o Embedded MPC8xx core with 105 MIPS at 80 MHz (using Dhrystone 2.1)\n? 4-Kbyte Instruction Cache\n? 4-Kbyte Data Cache\n? 8 Kb Dual Port RAM\n? Instruction and Data MMUs\n? Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)\n? 32 Address Lines\n? Complete Static Design (0-80 MHz Operat;

恩XP

PowerQUICC, 32 Bit Power Architecture SoC, 50MHz, CPM, ENET, ATM, HDLC, PCMCIA, -40 to 95C

The MPC855T is a versatile one-chip integrated microprocessor and peripheral combination designed for lower cost access equipment that requires fast ethernet support capable of 100 Mbps. This member of the MPC860 PowerQUICC? family combines an MPC8xx core processor along with 恩XP? Semiconductors's o Embedded MPC8xx core with 105 MIPS at 80 MHz (using Dhrystone 2.1)\n? 4-Kbyte Instruction Cache\n? 4-Kbyte Data Cache\n? 8 Kb Dual Port RAM\n? Instruction and Data MMUs\n? Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)\n? 32 Address Lines\n? Complete Static Design (0-80 MHz Operat;

恩XP

PowerQUICC, 32 Bit Power Architecture SoC, 66MHz, CPM, ENET, ATM, HDLC, PCMCIA, -40 to 95C

The MPC855T is a versatile one-chip integrated microprocessor and peripheral combination designed for lower cost access equipment that requires fast ethernet support capable of 100 Mbps. This member of the MPC860 PowerQUICC? family combines an MPC8xx core processor along with 恩XP? Semiconductors's o Embedded MPC8xx core with 105 MIPS at 80 MHz (using Dhrystone 2.1)\n? 4-Kbyte Instruction Cache\n? 4-Kbyte Data Cache\n? 8 Kb Dual Port RAM\n? Instruction and Data MMUs\n? Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)\n? 32 Address Lines\n? Complete Static Design (0-80 MHz Operat;

恩XP