MPC850DEVR50BU中文資料PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, 0 to 95C數(shù)據(jù)手冊恩XP規(guī)格書

描述 Description

The MPC850 PowerQUICC? processor offers a versatile, integrated, low-cost solution for variety of controller, networking, and communications applications.
Includes extensive communications and system integration support
Simplifies development and accelerates time-to-market
Offloads core tasks for increased performance and efficiency
Backed by strong third-party tool support through Our Design Alliance Program

特性 Features

Embedded MPC8xx Core with 87 MIPS at 66 MHz (using Dhrystone 2.1)
? 2-Kbyte Instruction Cache
? 1-Kbyte Data Cache
? Instruction and Data MMUs
? Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
? 26 External Address Lines
? Complete Static Design (0-66 MHz Operation)
? Memory Controller (Eight Banks)
? General-Purpose Timers
? System Integration Unit (SIU)
? Interrupts
? Communications Processor Module (CPM)
? Four Baud Rate Generators
? Up to two SCCs (Serial Communication Controller with Ethernet Support)
? One USB Port
? Two SMCs (Serial Management Channels)
? One SPI (Serial Peripheral Interface)
? One I2C (Inter-Integrated Circuit) Port
? Time-Slot Assigner
? Parallel I/O Ports (supports UTOPIA)
? PCMCIA Interface
? Low Power Support
? Debug Interface
? 3.3 V Operation
? 3.3 V System Bus Operation
? 256-Pin Ball Grid Array (BGA)