MPC8343EVRAGDB中文資料PowerQUICC, 32 Bit Power Arch SoC, 400MHz, DDR1/2, PCI, 1GbE, USB, SEC, 0 to 105C, Rev 2數(shù)據(jù)手冊恩XP規(guī)格書

描述 Description

The MPC8343E PowerQUICC? II? Pro integrated communications processor is a next-generation extension of the popular PowerQUICC II line. Based on a system-on-chip (SoC) architecture, the MPC8343E PowerQUICC II Pro?integrates the enhanced e300 core and advanced features, such as DDR memory, Dual Gigabit Ethernet, Dual PCI and Hi-Speed USB controllers. With clock speeds scaling to?400 MHz, the MPC8343E processor offers the highest performing PowerQUICC II devices available.
The MPC8343E PowerQUICC II Pro is designed to provide a cost-effective, highly integrated control processing solution that addresses the emerging needs of networking, communications and pervasive computing applications. MPC8343E processor can be used in applications such as Ethernet routers and switches, wireless LAN (WLAN) equipment, network storage, home network appliances, industrial control equipment, and copiers, printers and other imaging systems.
e300 SoC PlatformThe MPC8343E PowerQUICC II Pro is based on the e300 SoC platform—making it easy and fast to add or remove functional blocks and develop additional SoC-based family members targeting emerging market requirements. At the heart of the e300 SoC platform is NXP? Semiconductors's e300 core built on Power Architecture technology. The e300 core is an enhanced version of the 603e Power Architecture core used in previous-generation PowerQUICC II processors. Enhancements include twice as much L1 cache (32 KB data cache and 32 KB instruction cache) with integrated parity checking, and other performance-enhancing features. The e300 core is completely software-compatible with existing 603e core-based products.
Integrated SecurityThe MPC8343E features a powerful integrated security engine derived from NXP Semiconductors's security coprocessor product line. The MPC8343E security engine supports DES, 3DES, MD-5, SHA-1, AES, and ARC-4 encryption algorithms, as well as a public key accelerator and an on-chip random number generator. The security engine is capable of single-pass encryption and authentication, as required by IPsec, IEEE? 802.11i standard and other security protocols.

特性 Features

e300 core operating from 266 MHz up to 400 MHz (enhanced version of 603e core with larger caches)
? Secure Communications Architecture leveraging Mocana's Device Security Framework technology
? 32-bit, high-performance superscalar core
? 1260 MIPS @?400 MHz
? Double-precision floating point, integer, load/store, system register, and branch processor units
? 32 KB data and 32 KB instruction cache with line locking support
? DDR1/DDR2 memory controller, up to 266 MHz data rate, with a 32-bit interface with ECC
? Dual PCI interfaces
? Dual 10/100/1000 Ethernet controllers
? Embedded security engine
? Dual Hi-Speed USB controllers
? Local bus controller
? Dual UART (DUART)
? Dual I2C interfaces (master or slave mode)
? Four-channel DMA controller
? Serial peripheral interface (SPI)
? General-purpose parallel I/O (GPIO)
? IEEE 1149.1 JTAG test access port
? Package: 672-pin, 35 mm x 35 mm TBGA (1 mm pitch)
? Process technology: 130 nm CMOS
? Voltage: 1.2V core voltage with 3.3V and 2.5V I/O

應用 Application

Secure Transaction and Retail Payments
?POS Printer