PowerQUICC II Integrated Communications Processor Hardware Specifications

文件：754.82 Kbytes 頁數(shù)：41 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

MPC826xA (HiP4) Family Hardware Specifications

文件：662.42 Kbytes 頁數(shù)：48 Pages

MOTOROLA

摩托羅拉

MPC826xA (HiP4) Family Hardware Specifications

文件：662.42 Kbytes 頁數(shù)：48 Pages

MOTOROLA

摩托羅拉

PQ II HIP4 NO-PB REV B

The MPC8260 PowerQUICC? II? is an advanced integrated communications processor designed for the telecommunications and networking markets.\nThe MPC8260 now offers floating point support.\nThe MPC8260 PowerQUICC II can best be described as the next generation MPC860 PowerQUICC?, providing higher perf System core microprocessor supporting frequencies of 133-300 MHz\n? 190 MIPS at 100 MHz (Dhrystone 2.1)\n? 505 MIPS at 266 MHz (Dhrystone 2.1)\n? 570 MIPS at 300 MHz (Dhrystone 2.1)\n? High-performance, superscalar microprocessor\n? Disable CPU mode\n? Supports the 恩XP? external L2 cache chip (MPC26;

恩XP

POWERQUICC II HIP4 REV B

The MPC8260 PowerQUICC? II? is an advanced integrated communications processor designed for the telecommunications and networking markets.\nThe MPC8260 now offers floating point support.\nThe MPC8260 PowerQUICC II can best be described as the next generation MPC860 PowerQUICC?, providing higher perf System core microprocessor supporting frequencies of 133-300 MHz\n? 190 MIPS at 100 MHz (Dhrystone 2.1)\n? 505 MIPS at 266 MHz (Dhrystone 2.1)\n? 570 MIPS at 300 MHz (Dhrystone 2.1)\n? High-performance, superscalar microprocessor\n? Disable CPU mode\n? Supports the 恩XP? external L2 cache chip (MPC26;

恩XP

POWERQUICC II HIP4 REV B

The MPC8260 PowerQUICC? II? is an advanced integrated communications processor designed for the telecommunications and networking markets.\nThe MPC8260 now offers floating point support.\nThe MPC8260 PowerQUICC II can best be described as the next generation MPC860 PowerQUICC?, providing higher perf System core microprocessor supporting frequencies of 133-300 MHz\n? 190 MIPS at 100 MHz (Dhrystone 2.1)\n? 505 MIPS at 266 MHz (Dhrystone 2.1)\n? 570 MIPS at 300 MHz (Dhrystone 2.1)\n? High-performance, superscalar microprocessor\n? Disable CPU mode\n? Supports the 恩XP? external L2 cache chip (MPC26;

恩XP