32 Bit Power Architecture, 200MHz, Integrated Host Processor, PCI, 0 to 105C

The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High in \n? 166-266 MHz RISC processor core\n? 32-bit PCI interface operating at up to 66 MHz\n? Memory controller offering SDRAM support up to 133 MHz operation, supportup to 2 GB\n? General Purpose I/O and ROM Interface Support\n? Two-channel DMA controller that supports chaining\n? Messaging unit with I2;

恩XP

32 Bit Power Architecture, 266MHz, Integrated Host Processor, PCI, 0 to 105C

The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High in ? 166-266 MHz RISC processor core\n? 32-bit PCI interface operating at up to 66 MHz\n? Memory controller offering SDRAM support up to 133 MHz operation, supportup to 2 GB\n? General Purpose I/O and ROM Interface Support\n? Two-channel DMA controller that supports chaining\n? Messaging unit with I2O ;

恩XP

32 Bit Power Architecture, 200MHz, Integrated Host Processor, PCI, 0 to 105C

The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High in ? 166-266 MHz RISC processor core\n? 32-bit PCI interface operating at up to 66 MHz\n? Memory controller offering SDRAM support up to 133 MHz operation, supportup to 2 GB\n? General Purpose I/O and ROM Interface Support\n? Two-channel DMA controller that supports chaining\n? Messaging unit with I2O ;

恩XP