32-bit load/store RISC architecture

Features The main features of the M?CORE are as follows: ? 32-bit load/store RISC architecture ? Fixed 16-bit instruction length ? 16-entry, 32-bit general-purpose register file ? Efficient 4-stage execution pipeline, hidden from application software ? Single-cycle instruction execution for

文件：3.2961 Mbytes 頁數(shù)：259 Pages

恩XP

32-Bit Microcontroller

Overview The 32-bit MMC2001 integrated processor is a charter member of the M·CORE family of microcontrollers. Representing a new vision in 32-bit microRISC processors, the M·CORE architecture delivers the power-sensitive, cutting-edge interrput/system performance that our customers demand. The proc \n ?M·CORE? Integer Processor\n\t \n\t?32-bit RISC architecture\n\t?Low power, high performance\n\t \n \n ?On-chip, 256-Kbyte ROM\n ?On-chip, 32-Kbyte SRAM with battery backup supply support\n ?Interrupt Controller\n\t \n\t?Support for up to 32 interrupt sources\n\t \n \n ?External Interface Module ;

恩XP

256KB Asynchronous Secondary Cache Module for PowerPC

The MPC2001 is designed to provide asynchronous 256KB L2 cache for the PowerPC 60x processors. The module is configured as 32K x 64 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses eight of Motorola’s MCM6206 CMOS RAMs. Eight write enables are provided for byte w

文件：88.31 Kbytes 頁數(shù)：4 Pages

MOTOROLA

摩托羅拉

All-in-One Flyback Controller with Integrated Primary and Secondary Synchronous Rectification Driver with Capacitive Isolation

文件：1.25949 Mbytes 頁數(shù)：31 Pages

MPS

美國芯源

90VAC~265VAC/50Hz/60Hz, 12V/5A Evaluation Board

文件：794.76 Kbytes 頁數(shù)：15 Pages

MPS

美國芯源