16 OUTPUT LOW SKEW CLOCK GENERATOR

Features ? 48-pin SSOP (300 mil) package ? On-chip PLL generates output clocks up to 90 MHz from a simple crystal or clock input ? 16 low-skew outputs ? Output skew less than 350 ps on rising edges ? Ability to configure as – 16 clocks at full-frequency – 12 at full and 4 at half-frequency

文件：346.35 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/mk74cg117a/marking.html">MK74CG117A；Package：SSOP；16 OUTPUT LOW SKEW CLOCK GENERATOR

Features ? 48-pin SSOP (300 mil) package ? On-chip PLL generates output clocks up to 90 MHz from a simple crystal or clock input ? 16 low-skew outputs ? Output skew less than 350 ps on rising edges ? Ability to configure as – 16 clocks at full-frequency – 12 at full and 4 at half-frequency

文件：346.35 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/mk74cg117a/marking.html">MK74CG117A；Package：SSOP；16 OUTPUT LOW SKEW CLOCK GENERATOR

Features ? 48-pin SSOP (300 mil) package ? On-chip PLL generates output clocks up to 90 MHz from a simple crystal or clock input ? 16 low-skew outputs ? Output skew less than 350 ps on rising edges ? Ability to configure as – 16 clocks at full-frequency – 12 at full and 4 at half-frequency

文件：346.35 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

PLL and 32-Output Clock Driver

Description The MK74ZD133 is a monolithic CMOS high speed clock driver that includes an on-chip PLL (Phase Locked Loop). Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 32 outputs can eliminate oscillators and multip

文件：116.4 Kbytes 頁數(shù)：8 Pages

ICST

PLL and 32-Output Clock Driver

Description The MK74ZD133 is a monolithic CMOS high speed clock driver that includes an on-chip PLL (Phase Locked Loop). Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 32 outputs can eliminate oscillators and multip

文件：116.4 Kbytes 頁數(shù)：8 Pages

ICST

PLL and 32-Output Clock Driver

Description The MK74ZD133 is a monolithic CMOS high speed clock driver that includes an on-chip PLL (Phase Locked Loop). Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 32 outputs can eliminate oscillators and multip

文件：116.4 Kbytes 頁數(shù)：8 Pages

ICST

PLL and 32-Output Clock Driver

Description The MK74ZD133 is a monolithic CMOS high speed clock driver that includes an on-chip PLL (Phase Locked Loop). Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 32 outputs can eliminate oscillators and multip

文件：116.4 Kbytes 頁數(shù)：8 Pages

ICST

PLL and 32-Output Clock Driver

Description The MK74ZD133 is a monolithic CMOS high speed clock driver that includes an on-chip PLL (Phase Locked Loop). Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 32 outputs can eliminate oscillators and multip

文件：116.4 Kbytes 頁數(shù)：8 Pages

ICST

Cylindrical Reed Sensors with M8 Thread

文件：55.95 Kbytes 頁數(shù)：4 Pages

MEDER

Cylindrical Reed Sensors with M8 Thread

文件：55.95 Kbytes 頁數(shù)：4 Pages

MEDER