CLOCK RECOVERY PLL

Features ? Long-term output jitter

文件：329.44 Kbytes 頁數(shù)：15 Pages

RENESAS

瑞薩

Clock Recovery PLL

The MK1575-01 is a clock recovery Phase-Locked Loop (PLL) designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to accept a low-frequency reference clock to generate a high-frequency data or graphics pixel clock. External loop filter components allo Long-term output jitter <2 nsec over 10 ?sec period\nExternal PLL clock feedback path enable \"zero delay\" I/O clock skew configuration\nSelectable internal feedback divider provides popular telecom and video clock frequencies (see tables below)\nCan optionally use external feedback divider to gene;

Renesas

瑞薩

CLOCK RECOVERY PLL

Features ? Long-term output jitter

文件：329.44 Kbytes 頁數(shù)：15 Pages

RENESAS

瑞薩

CLOCK RECOVERY PLL

Features ? Long-term output jitter

文件：329.44 Kbytes 頁數(shù)：15 Pages

RENESAS

瑞薩

CLOCK RECOVERY PLL

Features ? Long-term output jitter

文件：329.44 Kbytes 頁數(shù)：15 Pages

RENESAS

瑞薩

CLOCK RECOVERY PLL

Features ? Long-term output jitter

文件：329.44 Kbytes 頁數(shù)：15 Pages

RENESAS

瑞薩

IC CLK DATA REC VIDEO 80MHZ

Renesas

瑞薩

IC CLK DATA REC VIDEO 80MHZ

Renesas

瑞薩

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK DATA REC VIDEO 80MHZ

Renesas Electronics America Inc

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK DATA REC VIDEO 80MHZ

Renesas Electronics America Inc